1. Field of the Invention
The present invention relates to a monolithic vertical-type semiconductor power device with a protection against parasitic currents.
2. Prior Art and Other Considerations
A vertical-type semiconductor integrated structure comprises essentially an N+ type substrate over which there is superimposed an N- type epitaxial layer in which there is obtained, a P type isolation pocket with protruding extremities, connected to ground. The isolation pocket contains N type regions which include P and N+ type regions which define circuit components of the device. On the bottom of the N regions there are also N+ type regions.
With the circuit's active components there are associated parasite components which switch on when the circuit's active components associated with them are switched on, and inject current in the central part of isolation pocket P.
The injected current flows through the isolation pocket and reaches the grounded metallic terminal.
If such terminal is far from the injection area, the isolation pocket itself rises in voltage since the resistive path which the current must follow to reach the grounded terminal is longer.
Such a voltage rise, which can be even of some volts, can jeopardize the operation of the integrated circuit.
In addition, in the case in which the N+ type substrate goes to a low voltage while the isolation pocket rises in voltage, a parasite junction diode between such regions enters into conduction injecting current into the substrate and thus jeopardizing the operation of the whole.
From such circuit behavior it is possible to understand the need for grounding pocket P at as many points as possible. Such problem is generally solved by connecting between them a substantial number of ground contacts on isolation pocket P by means of a metal track which is then grounded. Such a process is that much more complicated the greater is the number of ground contacts made and requires a substantial size since the metal ground tracks must be compatible with the several connection tracks of the different circuit elements.
The object of the present invention is to overcome the abovementioned drawbacks caused by the presence of selective ground contacts of the isolation pocket.